For electronic components, bare chip mounting that allows the mounting area to be remarkably reduced in comparison to conventional semiconductor packages has been in use. Under this condition, face-down mounting is widely used in which a circuit formation surface of a semiconductor chip (semiconductor device) and a circuit formation surface of a board are placed face to face and laid on each other via bumps (bump electrodes) formed of gold or other metal so as to obtain conduction. The face-down mounting allows a semiconductor chip as well as its whole mounted structure to be further downsized, compared with face-up mounting in which a circuit formation surface of a board and a surface of a semiconductor chip counter to its circuit formation surface are placed face to face and, in this state, metal thin wires are led out by wire bonding so that both-side terminals are connected to each other.
Among others, the sheet bonding technique in which bumps formed on pads of the semiconductor chip and the board having sheet-like seal-bonding resin stuck on its surface are set face to face and pressed to each other makes it possible to simultaneously carry out the filling of the seal-bonding resin between semiconductor chip and board and the connection of the pads of the semiconductor chip and the electrodes of the board, thus being effective for process simplification and time reduction and being in widespread use.    Patent Literature 1: JP 2003-109988 A    Patent Literature 2: JP 2005-32952 A
In recent years, advancements have been being made toward lower dielectric constants of insulating material inside the chip with a view to scaling-down of chip-inside interconnections for size and cost reductions of semiconductor packages. With regard to such low-dielectric-constant insulating materials (hereinafter, referred to as “low-k materials”), as the dielectric constant decreases, the insulating material becomes more fragile in terms of mechanical strength, posing a fear of internal breakdown of semiconductor chips caused by the fragility of low-k materials in semiconductor chip mounting process.
In general, the coefficient of thermal expansion of a semiconductor chip is extremely smaller than those of seal-bonding resin (underfill) and the board. Therefore, thermal expansion differences or thermal contraction differences among the individual members caused by heating and cooling in a mounting operation cause large stress loads to be generated at portions of the semiconductor chip. Particularly at corner portions of a rectangular-shaped semiconductor chip, the stuck sheet-like seal-bonding resin does not flow out enough, so that side faces of the semiconductor chip are exposed. Therefore, stress loads at the corner portions have a larger effect, causing a likelihood that cracks or peeling may occur after the mounting.
In order to reduce these and other loads, for example, Patent Literature 1 shows a method in which sealing resin flowing out during the press of the semiconductor chip is blocked with a metallic tool having a metallic protruding portion used for the pressing of the semiconductor chip, thus making it easier to form a fillet portion (foot expanding portion) around the semiconductor chip. However, in the method of Patent Literature 1, the metallic tool cannot permit variations in configuration and posture and the like of the board or positional shifts of the semiconductor chip, giving rise to a problem that the fillet portion becomes unstable in terms of variations. On the other hand, Patent Literature 2 proposes a method in which not a metallic tool but an elastic member tool typified by a rubber one is used as the tool for pressing the semiconductor chip so that the seal-bonding resin around the semiconductor chip is heated and hardened by the elastic member, thus allowing the fillet portion to be formed stably around the semiconductor chip. However, in the method of Patent Literature 2, the fillet amount (resin amount) of corners of the semiconductor chip is not enough with side faces of the semiconductor chip not covered but exposed as well, so that the semiconductor chip cannot be protected enough. Moreover, deformation of the elastic member inhibits enough loads from being transferred to the semiconductor chip, posing a fear that inter-electrode junction cannot be secured.